SPRxDATA/SPRxDATB
Address Name Description
DFF144 SPR0DATA Sprite 0 image data register A
DFF146 SPR0DATB Sprite 0 image data register B
DFF14C SPR1DATA Sprite 1 image data register A
DFF14E SPR1DATB Sprite 1 image data register B
DFF154 SPR2DATA Sprite 2 image data register A
DFF156 SPR2DATB Sprite 2 image data register B
DFF15C SPR3DATA Sprite 3 image data register A
DFF15E SPR3DATB Sprite 3 image data register B
DFF164 SPR4DATA Sprite 4 image data register A
DFF166 SPR4DATB Sprite 4 image data register B
DFF16C SPR5DATA Sprite 5 image data register A
DFF16E SPR5DATB Sprite 5 image data register B
DFF174 SPR6DATA Sprite 6 image data register A
DFF176 SPR6DATB Sprite 6 image data register B
DFF17C SPR7DATA Sprite 7 image data register A
DFF17E SPR7DATB Sprite 7 image data register B

Overview

These registers buffer the sprite image data. They are usually loaded
by the sprite DMA channel but may be loaded by either processor at
any time. When a horizontal coincidence occurs the buffers are dumped
into shift registers and serially outputted to the display, MSB first
on the left.

Note:
Writing to the A buffer enables (arms) the sprite.
Writing to the SPRxCTL registers disables the sprite.
If enabled, data in the A and B buffers will be output whenever the
beam counter equals the sprite horizontal position value in the
SPRxPOS register. In lowres mode, 1 sprite pixel is 1 bitplane pixel
wide.In HRES and SHRES mode, 1 sprite pixel is 2 bitplane pixels.
The DATB bits are the 2SBs (worth 2) for the color registers,
and MSB for SHRES. DATA bits are LSBs of the pixels.

This material is most likely derived from the official Amiga documentation and where applicable copyright remains with the original author.