COPINS

Address Name Description DFF08C COPINS Coprocessor instruction fetch identity

Overview

This is a dummy address that is generated by the coprocessor whenever
it is loading instructions into its own instruction register.
This actually occurs every coprocessor cycle except for the second
(IR2) cycle of the MOVE instruction. The three types of instructions
are shown below.

MOVE Move immediate to dest WAIT Wait until beam counter is equal to, or greater than. (Keeps coprocessor off of bus until beam position has been reached) SKIP Skip if beam counter is equal to, or greater than. (Skips following MOVE inst. unless beam position has been reached)

MOVE WAIT UNTIL SKIP IF Bit IR1 IR2 IR1 IR2 IR1 IR2 15 0 RD15 VP7 BFD VP7 BFD 14 0 RD14 VP6 VE6 VP6 VE6 13 0 RD13 VP5 VE5 VP5 VE5 12 0 RD12 VP4 VE4 VP4 VE4 11 0 RD11 VP3 VE3 VP3 VE3 10 0 RD10 VP2 VE2 VP2 VE2 09 0 RD09 VP1 VE1 VP1 VE1 08 DA8 RD08 VP0 VE0 VP0 VE0 07 DA7 RD07 HP8 HE8 HP8 HE8 06 DA6 RD06 HP7 HE7 HP7 HE7 05 DA5 RD05 HP6 HE6 HP6 HE6 04 DA4 RD04 HP5 HE5 HP5 HE5 03 DA3 RD03 HP4 HE4 HP4 HE4 02 DA2 RD02 HP3 HE3 HP3 HE3 01 DA1 RD01 HP2 HE2 HP2 HE2 00 0 RD00 1 0 1 1

IR1 First instruction register IR2 Second instruction register DA Destination address for MOVE instruction.Fetched during IR1 time,used during IR2 time on RGA bus RD RAM Data moved by MOVE instruction at IR2 time directly from RAM to the address given by the DA field VP Vertical beam position comparison bit HP Horizontal beam position comparison bit VE Enable comparison (mask bit) HE Enable comparison (mask bit)

Note: BFD = Blitter finished disable. When this bit is true, the blitter finished flag will have no effect on the coprocessor. When this bit is zero the blitter finished flag must be true (in addition to the rest of the bit comparisons) before the coprocessor can exit from it`s wait state, or skip over an instruction. Note that the V7 comparison cannot be masked.

The coprocessor is basically a 2 cycle machine that requests
the bus only during odd memory cycles. (4 memory cycles per in)

It has priority over the blitter and microprocessor.

There are only three types of instructions, MOVE immediate,
WAIT UNTIL, and SKIP IF. All instructions require 2 bus cycles
(and two instruction words). Since only the odd bus cycles are
requested, 4 memory cycle times are required per instruction.
(memory cycles are 280 ns).

There are two indirect jump registers COP1LC and COP2LC.
These are 20 bit pointer registers whose contents are used to modify
program counter for initialization or jumps.

They are transfered to the program counter whenever strobe address
COPJMP1 or COPJMP2 are written. In addition COP1LC is automatically
used at the beginning of each vertical blank time.

It is important that one of the jump registers be initialized and it`s
jump strobe address hit, after power up but before coprocessor DMA is
initialized. This insures a determined startup address, and state.

• COP1LCH/COP1LCL
• COP2LCH/COP2LCL
• Hardware