This bit is used to disable the hardwired vertical horizontal
window limits. It is cleared upon reset.
When this bit is a low and LPE (BPLCON0, bit 3) is enabled, the
light-pen latched value(beam hit position) will be read by
VHPOSR, VPOSR and HHPOSR. When the bit is a high the light-pen
latched value is ignored and the actual beam counter position is
read by VHPOSR, VPOSR, and HHPOSR.
Use the comparator generated vertical blank (from VBSTRT, VBSTOP)
to run the internal chip stuff-sending RGA signals to Denise,
starting sprites,resetting light pen. It also disables the hard
stop on the vertical display window.
Disable long line/short toggle. This is useful for DUAL mode
where even multiples are wanted, or in any single display
where this toggling is not desired.
The variable composite sync comes out on the HSY pin, and the
variable composite blank comes out on the VSY pin. The idea is
to allow all the information to come out of the chip for a
DUAL mode display. The normal monitor uses the normal composite
sync, and the variable composite sync &blank come out the HSY &
VSY pins. The bits VARVSTEN & VARHSYEN (below) have priority over
this control bit.
Comparator VSY -> VSY pin. The variable VSY is set vertically on
VSSTRT, reset vertically on VSSTOP, with the horizontal position
for set set & reset HSSTRT on short fields (all fields are short
if LACE = 0) and HCENTER on long fields (every other field if LACE = 1).
Enables the variable beam counter comparators to operate
(allowing different beam counter total values) on the main horiz
counter. It also disables hard display stops on both horizontal
Run the horizontal comparators with the alternate horizontal beam
counter, and starts the UHRES pointer chain with the reset of
this counter rather than the normal one. This allows the UHRES
pointers to come out more than once in a horizontal line,
assuming there is some memory bandwidth left (it doesn't work in
640*400*4 interlace mode) also, to keep the two displays synced,
the horizontal line lengths should be multiples of each other.
If you are amazingly clever, you might not need to do this.
Set appropriate decodes (in normal mode) for PAL. In variable
beam counter mode this bit disables the long line/short line
toggle- ends up short line.
Enables CSY from the variable decoders to come out the CSY
(VARCSY is set on HSSTRT match always, and also on HCENTER
match when in vertical sync. It is reset on HSSTOP match when VSY
and on both HBSTRT & HBSTOP matches during VSY. A reasonable
composite can be generated by setting HCENTER half a horizontal line
from HSSTRT, and HBSTOP at (HSSTOP-HSSTRT) before HCENTER, with
HBSTRT at ( HSSTOP-HSSTRT) before HSSTRT.
HSYTRUE, VSYTRUE, CSYTRUE
These change the polarity of the HSY*, VSY*, & CSY* pins
to HSY, VSY, & CSY respectively for input and output.